1. Technical Field
The present invention relates in general to a circuit and method for providing a numeric indication of the number of leading zeros in a binary data word. In particular, the present invention relates to a circuit and method for providing a corrected data word value for a leading zeros count with a more efficient component structure.
2. Description of the Related Art
Modern data processing systems use binary numbers for the computation of data. This computation includes both integer arithmetic and floating-point arithmetic. One common operation that is used in floating-point arithmetic, is determining the number of leading zeros in a data word for normalization, i.e., for removing the zeroes just past the decimal point such that the first bit after the decimal point is a “1”. Special circuitry has been devised to determine perform this function and is illustrated in U.S. Pat. No. 5,844,826 entitled “Leading Zero Count Circuit.” Another example of a count leading zero specialized circuit will be discussed in this application. Other applications where this function may be useful would be where the data format is monotonic, i.e., where data is a series of consecutive ‘0’s followed by a series of consecutive ‘1’s as may be generated by a mask generator, successive approximation A/D converter, or a chain of inverters as described in this application.
In a co-pending patent application entitled “On-Chip Frequency Response Measurement” U.S. patent application Ser. No. 11/844,393 now U.S. Pat. No. 7,797,131 also assigned to IBM and herein incorporated by reference, the count leading zeros function is used as part of a frequency response measurement circuit. The function of this count leading zeros circuit is the same as the count leading zeros circuit function and floating-point arithmetic applications. Also in a co-pending patent application entitled “Half Width Counting Leading Zero Circuit” U.S. patent application Ser. No. 11/844,402 also assigned to IBM and herein incorporated by reference, a more efficient count leading zero circuit is disclosed which can be used as part of the frequency response measurement circuit.
This frequency measurement circuit is used as part of a larger apparatus that determines certain physical characteristics of an operating integrated circuit. This larger apparatus provides a scaled voltage to the integrated circuited itself and is to the disclosed in co-pending patent applications entitled “Using IR Drop Data for Instruction Thread Direction,” U.S. patent application Ser. No. 11/671,613, “On-Chip Adaptive Voltage Compensation,” U.S. patent application Ser. No. 11/671,485 now U.S. Pat. No. 7,936,153; “Using Performance Data for Instruction Thread Direction,” U.S. patent application Ser. No. 11/671,627 now U.S. Pat. No. 7,779,235; “Using Temperature Data for Instruction Thread Direction,” U.S. patent application Ser. No. 11/671,640; “Integrated Circuit Failure Prediction,” U.S. patent application Ser. No. 11/671,599 now U.S. Pat. No. 7,560,945; “Instruction Dependent Dynamic Voltage Compensation,” U.S. patent application Ser. No. 11/671,579 now U.S. Pat. No. 7,895,454; “Temperature Dependent Voltage Source Compensation,” U.S. patent application Ser. No. 11/671,568; “Fan Speed Control from Adaptive Voltage Supply,” U.S. patent application Ser. No. 11/671,555 now U.S. Pat. No. 7,865,750; and “Digital Adaptive Voltage Supply,” U.S. patent application Ser. No. 11/671,531 now U.S. Pat. No. 7,714,635; each assigned to the IBM Corporation and herein incorporated by reference.
As can be seen by the examination of the U.S. Pat. No. 5,844,826, the circuitry to provide this count leading zeros function is complex. In order to provide a simpler and more efficient count leading zeros circuit, the data input into such a count leading zeros must be corrected to remove any errors caused by circuit timing differences to provide the correct input data.